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1 smbus level 2 battery charger isl88731c the isl88731c is a highly integrated lithium-ion battery charger controller, programmable over the smbus system management bus (smbus). the is l88731c is intended to be used in a smart battery charger (sbc) within a smart battery system (sbs) that throttles the charge power such that the current from the ac-adapter is automatically limited. high efficiency is achieved with a dc/dc synchronous-rectifier buck converter, equipped with diode emulation for enhanced light load efficiency and system bus boosting prevention. the isl88731c charges one to four lithium-ion series cells, and delivers up to 8a charge current. integrated mosfet drivers and bootstrap diode result in fewer components and smaller implementation area. low offset current-sense amplifiers provide high accuracy with 10m sense resistors. the isl88731c provides 0.5% end-of-charge battery voltage accuracy. the isl88731c provides a digita l output that indicates the presence of the ac adapter as we ll as an analog output which indicates the adapter current within 4% accuracy. the isl88731c is available in a small 5mmx5mm 28 ld thin (0.8mm) qfn package. an evaluation kit is available to reduce design time. the isl88731c is available in pb-free packages. related literature ?see an1404 for ?isl88731eval2z and ISL88731CEVAL2Z evaluation boards setup procedure? features ? 0.5% battery voltage accuracy ? 3% adapter current limit accuracy ? 3% charge current accuracy ? smbus 2-wire serial interface ? battery short circuit protection ? fast response for pulse-charging ? fast system-load transient response ? monitor outputs - adapter current (3% accuracy) - ac-adapter detection ? 11-bit battery voltage setting ? 6 bit charge current/adapter current setting ? 8a maximum battery charger current ? 11a maximum adapter current ? +8v to +26v adapter voltage range ? pb-free (rohs compliant) applications ? notebook computers ?tablet pcs ? portable equipment with rechargeable batteries figure 1. typical charging voltage and current figure 2. efficiency vs charge current and battery voltage charge time (minutes) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 0 20 40 60 80 100 120 140 160 battery voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 battery current vchg (v) ichg (a) 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 i out (a) efficiency (%) 8.4v battery 12.6v battery 16.8v battery 4.2v battery caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. june 8, 2011 fn6978.3
isl88731c 2 fn6978.3 june 8, 2011 figure 3. functional block diagram smbus vddsmb dc/dc converter sda vfb csop phase lgate ugate boot pgnd vddp lvb scl + - gmv + - gmi daci dacs dacv + - gms level shifter 20x level shifter 20x cson cssp cssn icomp vcomp vcc 11 6 6 dacs daci dacv dacs daci dacv lvb reference linear regulator dcin vref + - acin acok 3.2v buff icm cssp en cso en gnd en vddp 100k 500k phase boot ugate lgate pgnd isl88731c cssn cssp csop cson acin scl vref dcin sda vddsmb icm icomp vcomp vcc acok vddp gnd ac adapter to battery to system host vfb rs1 rs2 agnd pgnd agnd figure 4. typical application circuit
isl88731c 3 fn6978.3 june 8, 2011 pin configuration isl88731c (28 ld tqfn) top view cssp cssn vcc boot ugate phase dcin icm sda scl vddsmb gnd acok nc nc acin vref icomp nc vcomp nc vddp lgate pgnd csop cson nc vfb 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 pd functional pin descriptions pin number symbol description 2 acin ac adapter detection input. connect to a resistor divider from the ac adapter output. range zero to 5.5v. 3 vref reference voltage output. range 3.168v to 3.232v. it is internally compensate d. do not connect a decoupling capacitor. 4 icomp compensation point for the charging current and adap ter current regulation loop. connect 0.01f to gnd. see ?voltage control loop? on page 21 for details on selecting the icomp capacitor. range zero to 5.5v. 6 vcomp compensation point for the vo ltage regulation loop. connect 4.7k in series with 0.01f to gnd. see ?voltage control loop? on page 21 for details on selecting vcomp components. range zero to 5.5v. 8 icm input current monitor output. icm voltage equals 20 x (v cssp - v cssn ). range zero to 3v. 9 sda smbus data i/o. open-drain output. connect an external pull-up resistor a ccording to smbus specifications. range zero to 5.5v. 10 scl smbus clock input. connect an external pull-up resist or according to smbus specifications. range zero to 5.5v. 11 vddsmb smbus interface supply voltage input. bypass wi th a 0.1f capacitor to gnd. range 3.3v to 5.5v. 12 gnd analog ground. connect directly to the backside paddle. connect to the backside paddle and pgnd at one point close to (under) the ic. 13 acok ac detect output. this open drain output is high impedanc e when acin is greater than 3.2v. the acok output remains low when the isl88731c is powered down. connect a 10k pull-up resistor from acok to vddsmb. range 3.3v to 5.5v. 15 vfb feedback for the battery voltage. range 1v to 19v. 17 cson charge current-sense negative input. range 1v to 19v. 18 csop charge current-sense positive input. range 1v to 19v. 19 pgnd power ground. connect pgnd to the source of the low side mosfet and the negative side of capacitors to the charger output and the drain of the upper switching fet. co nnect this area to the backside paddle at one location very near (under) the ic. 20 lgate low-side power mosfet driver output. connect to lo w-side n channel mosfet. lgate drives between vddp and pgnd. range is -0.3v to 5.23v.
isl88731c 4 fn6978.3 june 8, 2011 21 vddp linear regulator output. vddp is the output of the 5. 2v linear regulator supplied from dcin. vddp also directly supplies the lgate driver and the boot strap diode. bypass with a 1f ceramic capacitor from vddp to pgnd. range is 5.0v to 5.23v. 22 dcin charger bias supply input. bypass dcin wi th a 0.1f capacitor to gnd. range 8v to +26v. 23 phase high-side power mosfet driver source connection. conne ct to the source of the high-side n-channel mosfet. range -2v to +26v. 24 ugate high-side power mosfet driver output. connect to the high-side n-channel mosfet gate. range -2v to +33v. 25 boot high-side power mosfet driver power-supply connecti on. connect a 0.1f capacitor from boot-to-phase. range -2v to +33v. 26 vcc power input for internal analog circuits. connect a 4.7 resistor from vcc to vddp and a 1f ceramic capacitor from vcc to ground. range 4v to 5.23v. 27 cssn input current-sense negative input. range 8v to 26v. 28 cssp input current-sense positive input. range 8v to 26v. pd connect the backside paddle to gnd. this pad has the lowest thermal resistance to the die. it should be connected to a large area of ground with 3 to 5 vias for good thermal performance. the recommended potential of the thermal pad is zero (0) volts. 1, 5, 7, 14, 16 nc no connect. pins are not connected internally. ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl88731chrtz 88731c hrtz -10 to +100 28 ld 5x5 tqfn l28.5x5b ISL88731CEVAL2Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl88731c . for more information on msl please see tech brief tb363 . functional pin descriptions (continued) pin number symbol description
isl88731c 5 fn6978.3 june 8, 2011 table of contents absolute maximum ratings ...................................................6 thermal information ...............................................................6 electrical specifications ........................................................6 smbus timing specifications.................................................8 typical operating performance ...................................................9 theory of operation ............................................................. 11 introduction ..................................................................................11 pwm control.................................................................................11 ac-adapter detection..................................................................11 current measurement.................................................................11 vddp regulator ...........................................................................11 vddsmb supply ...........................................................................11 short circuit protection and 0v battery charging ..................11 undervoltage detect and batte ry trickle charging ................11 over-temperature protection ....................................................12 overvoltage protection ...............................................................12 the system management bus...................................................12 general smbus architecture......................................................12 data validity .................................................................................12 start and stop conditions..............................................................12 acknowledge.........................................................................................13 smbus transactions............................................................................13 byte format .......................................................................... 13 isl88731c and smbus ......................................................... 13 battery charger registers................................................... 14 enabling and disabling charging........................................ 14 setting charge voltage........................................................ 14 setting charge current ........................................................ 15 setting input-current limit.................................................. 16 charger timeout ....................................................................17 isl88731c data byte order ..................................................17 writing to the internal registers .........................................17 reading from the internal registers...................................17 application information .......................................................17 inductor selection ....................................................................... 17 output capacitor selection ........................................................ 18 mosfet selection ....................................................................... 18 snubber design ........................................................................... 19 input capacitor selection........................................................... 19 loop compensation design....................................................... 19 transconductance amplifiers gmv, gmi and gms ................ 19 pwm gain fm .............................................................................. 19 charge current control loop ..................................................... 20 adapter current limit control loop.......................................... 20 voltage control loop................................................................... 21 output lc filter transfer functions .......................................... 21 compensation break frequency equations ............................ 22 pcb layout considerations................................................. 22 power and signal layers placement on the pcb ................... 22 component placement............................................................... 22 signal ground and power ground connection........................ 22 gnd and vcc pin......................................................................... 22 lgate pin ..................................................................................... 22 pgnd pin ...................................................................................... 22 phase pin .................................................................................... 23 ugate pin..................................................................................... 23 boot pin....................................................................................... 23 csop, cson, cssp and cssn pins .......................................... 23 dcin pin........................................................................................ 23 copper size for the phase node ............................................... 23 identify the power and signal ground ..................................... 23 clamping capacitor for switching mosfet............................. 23 revision history ................................................................... 24 products................................................................................ 24 package outline drawing .................................................... 25
isl88731c 6 fn6978.3 june 8, 2011 absolute maximum rating s thermal information dcin, cssp, cssn, csop, cson, vfb . . . . . . . . . . . . . . . . . . . -0.3v to +28v cssp-cssn, csop-cson, pgnd-gnd . . . . . . . . . . . . . . . . . . -0.3v to +0.3v phase to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +30v boot to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v ugate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phase - 0.3v to boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pgnd - 0.3v to vddp + 0.3v icomp, vcomp, vref, to gnd . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v vddsmb, scl, sda, acin, acok . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vddp, icm, vcc to gnd, vddp to pgnd . . . . . . . . . . . . . . . . . . -0.3v to +6v thermal resistance (typical) ja (c/w) jc (c/w) 28 ld tqfn package (notes 4, 5) . . . . . . . 38 6.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . . -55 c to +150c operating temperature range . . . . . . . . . . . . . . . . . . . . . . -10 c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications dcin = cssp = cssn = 18v, csop = cson = 12v, vddp = 5v, boot-phase = 5.0v, gnd = pgnd = 0v, cvddp = 1f, ivddp = 0ma, t a = -10c to +100c. boldface limits apply over the operat ing temperature range, -10c to +100c . parameter conditions min (note 7) typ max (note 7) units charge voltage regulation battery full charge voltage and accuracy chargevoltage = 0x41a0 16.716 16.8 16.884 v -0.5 0.5 % chargevoltage = 0x3130 12.529 12.592 12.655 v -0.5 0.5 % chargevoltage = 0x20d0 8.350 8.4 8.450 v -0.6 0.6 % chargevoltage = 0x1060 4.163 4.192 4.221 v -0.7 0.7 % battery undervoltage lockout trip point for trickle charge vfb rising 2.55 2.7 2.85 v battery undervoltage lockout trip point hysteresis 100 250 400 mv charge current regulation csop to cson full-scale current-sense voltage 78.22 80.64 83.06 mv charge current and accuracy rs2 = 10m (see figure 4) chargingcurrent = 0x1f80 7.822 8.064 8.306 a -3 3 % rs2 = 10m (see figure 4) chargingcurrent = 0x0f80 3.809 3.968 4.126 a -4 4 % rs2 = 10m (see figure 4) chargingcurrent = 0x0080 64 128 220 ma charge current gain error based on charge current = 128ma and 8.064a -1.6 1.4 % csop/cson input voltage range 019 v
isl88731c 7 fn6978.3 june 8, 2011 battery quiescent current adapter present, not charging, i csop + i cson + i phase + i cssp + i cssn + i fb v phase = v cson = v csop = v dcin = 19v, v acin = 5v 135 200 a adapter absent i csop + i cson + i phase + i cssp + i cssn + i fb v phase = v cson = v csop = 19v, v dcin = 0v -1 0.2 2 a adapter quiescent current i dcin + i cssp + i cssn vadapter = 8v to 26v, vbattery 4v to 16.8v 3 5 ma input current regulation cssp to cssn full-scale current-sense voltage cssp = 19v 106.7 110 113.3 mv input current accuracy rs1 = 10m (see figure 4) adapter current = 11004ma or 3584ma -3 3 % rs1 = 10m (see figure 4) adapter current = 2048ma -5 5 % input current limit gain error based on inputcurrent = 1024ma and 11004ma -1.5 1.5 % input current limit offset -1 1 mv cssp/cssn input voltage range 826 v icm gain v cssp-cssn = 110mv 20 v/v icm accuracy v cssp-cssn = 110mv -2.5 2.5 % v cssp-cssn = 55mv or 35mv -4 4 % v cssp-cssn = 20mv -8 8 % icm max output current v cssp-cssn = 0.1v 500 a supply and linear regulator dcin, input voltage range 826 v vddp output voltage 8.0v < v dcin < 28v, no load 5.0 5.1 5.23 v vddp load regulation 0 < i vddp < 30ma 35 100 mv vddsmb range 2.7 5.5 v vddsmb uvlo rising 2.4 2.5 2.6 v vddsmb uvlo hysteresis 40 100 150 mv vddsmb quiescent current vddp = scl = sda = 5.5v 20 27 a v reference vref output voltage 0 < i vref < 300a 3.168 3.2 3.232 v acok acok sink current v acok = 0.4v, acin = 1.5v 2 8ma acok leakage current v acok = 5.5v, acin = 3.7v 1 a acin acin rising threshold 3.15 3.2 3.25 v acin threshold hysteresis 40 60 90 mv acin input bias current -1 1 a electrical specifications dcin = cssp = cssn = 18v, csop = cson = 12v, vddp = 5v, boot-phase = 5.0v, gnd = pgnd = 0v, cvddp = 1f, ivddp = 0ma, t a = -10c to +100c. boldface limits apply over the operat ing temperature range, -10c to +100c . (continued) parameter conditions min (note 7) typ max (note 7) units
isl88731c 8 fn6978.3 june 8, 2011 switching regulator frequency 330 400 440 khz boot supply current ugate high 170 290 400 a phase input bias current v dcon = 28v, v cson = v phase = 20v 0 2 a ugate on-resistance low i ugate = -100ma 0.9 1.6 ugate on-resistance high i ugate = 10ma 1.4 2.5 lgate on-resistance high i lgate = +10ma 1.4 2.5 lgate on-resistance low i lgate = -100ma 0.9 1.6 dead time falling ugate to rising lgate or falling lgate to rising ugate 35 50 80 ns error amplifiers gmv amplifier transconductance 200 250 300 a/v gmi amplifier transconductance 40 50 60 a/v gms amplifier transconductance 40 50 60 a/v gmi/gms saturation current 15 21 25 a gmv saturation current 10 17 30 a icomp, vcomp clamp voltage 0.25v < v icomp, vcomp < 3.5v 200 300 400 mv logic levels sda/scl input low voltage vddsmb = 2.7v to 5.5v 0.8 v sda/scl input high voltage vddsmb = 2.7v to 5.5v 2 v sda/scl input bias current vddsmb = 2.7v to 5.5v -1 1 a sda, output sink current v sda = 0.4v 7 15 ma electrical specifications dcin = cssp = cssn = 18v, csop = cson = 12v, vddp = 5v, boot-phase = 5.0v, gnd = pgnd = 0v, cvddp = 1f, ivddp = 0ma, t a = -10c to +100c. boldface limits apply over the operat ing temperature range, -10c to +100c . (continued) parameter conditions min (note 7) typ max (note 7) units smbus timing specifications vddsmb = 2.7v to 5.5v. parameter symbol conditions min typ max units smbus frequency fsmb 10 100 khz bus free time t buf 4.7 s start condition hold time from scl t hd:sta 4s start condition setup time from scl t su:sta 4.7 s stop condition setup time from scl t su:sto 4s sda hold time from scl t hd:dat 300 ns sda setup time from scl t su:dat 250 ns scl low timeout (note 6) t timeout 22 25 30 ms scl low period t low 4.7 s scl high period t high 4s maximum charging period without an smbus write to chargevoltage or chargecurrent register 140 180 220 s notes: 6. if scl is low for longer than the specified time, the charger is disabled. 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested.
isl88731c 9 fn6978.3 june 8, 2011 typical operating performance dcin = 20v, 3s2p li-battery, t a = +25c, unless otherwise noted. figure 5. vdd load regulation figure 6. vref load regulation figure 7. icm accuracy vs ac-adapter current figure 8. typical charging voltage and current figure 9. charge enable figure 10. charge disable 4.85 4.90 4.95 5.00 5.05 5.10 5.15 020 4060 80100 vddp load current (ma) vddp (v) 3.17 3.18 3.19 3.20 3.21 3.22 3.23 0 50 100 150 200 i vref (a) vref (v) -1.0% -0.5% 0.0% 0.5% 1.0% -15 -10 -5 0 5 10 15 12 3 5 6 7 ac-adapter current (a) icm accuracy (%) 48 10.0 10.5 11.0 11.5 12.0 12.5 13.0 0 20 40 60 80 100 120 140 160 time (minutes) battery voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 battery current vchg (v) ichg (a) vcomp icomp inductor current charge current vcomp icomp inductor current charge current
isl88731c 10 fn6978.3 june 8, 2011 figure 11. switching waveforms at diode emul ation figure 12. switching waveforms in cc mode figure 13. battery removal figure 14. battery insertion figure 15. load transient response figure 16 . efficiency vs charge current and battery voltage typical operating performance dcin = 20v, 3s2p li-battery, t a = +25c, unless otherwise noted. (continued) ugate lgate inductor current phase ugate lgate inductor current phase cson/ v battery battery current battery current cson/ v battery system load battery voltage charge current adapter current 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 i out (a) efficiency (%) 8.4v battery 12.6v battery 16.8v battery 4.2v battery
isl88731c 11 fn6978.3 june 8, 2011 theory of operation introduction the isl88731c includes all of the functions necessary to charge 1 to 4 cell li-ion and li-polymer batteries. a high efficiency synchronous buck converter is used to control the charging voltage up to 19.2v and char ging current up to 8a. the isl88731c also has input current limiting up to 11a. the input current limit, charge current limi t and charge volt age limit are set by internal registers written with smbus. the isl88731c ?typical application circuit? is shown in figure 4. the isl88731c charges the battery with constant charge current, set by the chargecurrent register, until the battery voltage rises to a voltage set by the chargevoltage register. the charger will then operate at a constant voltage. the adapter current is monitored and if the adapter current rises to the limit set by the inputcurrent register, battery charge current is reduced so the charger does not reduce the adapter current available to the system. the isl88731c features a voltage regulation loop (vcomp) and 2 current regulation loops (icomp). the vcomp voltage regulation loop monitors vfb to limit the battery charge voltage. the icomp current regulation loop limits the battery charging current delivered to the battery to ensure that it never exceeds the current set by the chargecurrent register. the icomp current regulation loop also limits the input current drawn from the ac-adapter to ensure that it never exceeds the limit set by the inputcurrent register, and to prevent a system crash and ac-adapter overload. pwm control the isl88731c employs a fixed frequency pwm control architecture with a feed-forwa rd function. the feed-forward function maintains a constant modula tor gain of 11 to achieve fast line regulation as the input voltage changes. the duty cycle of the buck regulator is controlled by the lower of the voltages on icomp and vcom p. the voltage on icomp and vcomp are inputs to a lower voltag e buffer (lvb) who?s output is the lower of the 2 inputs. the output of the lvb is compared to an internal 400khz ramp to produce the pulse width modulated signal that controls the ugate and lgate drivers. an internal clamp holds the higher of the 2 voltages (0.3v) above the lower voltage. this speeds the transition from voltage loop control to current loop control or vice versa. the isl88731c can operate up to 99.6% duty cycle if the input voltage drops close to or below the battery charge voltage (drop out mode). the dc/dc converter has a timer to prevent the frequency from dropping into the audible frequency range. to prevent boosting of the system bus voltage, the battery charger drives the lower fet in a way that prevents negative inductor current. an adaptive gate drive scheme is used to control the dead time between two switches. the dead ti me control circuit monitors the lgate output and prevents the up per side mosfet from turning on until 20ns after lgate falls below 1v v gs , preventing cross-conduction and shoot-throu gh. the same occurs for lgate turn on. in order for the deadtime circuit to work properly, there must be a low resistance, low inductance path from the lgate driver to mosfet gate, and from the source of mosfet to pgnd. an internal schottky diode between the vddp pin and boot pin keeps the bootstrap capacitor charged. ac-adapter detection connect the ac-adapter voltage through a resistor divider to acin to detect when ac power is available, as shown in figure 4. acok is an open-drain output and is active low when acin is less than v th,fall , and high when acin is above v th,rise . the acin rising threshold is 3.2v (typ) with 60mv hysteresis. current measurement use icm to monitor the adapter current being sensed across cssp and cssn. the output voltage range is 0v to 2.5v. the voltage of icm is proportional to the voltage drop across cssp and cssn, and is given by equation 1: where i adapter is the dc current drawn from the ac adapter. it is recommended to have an rc filter at the icm output for minimizing the switching noise. vddp regulator vddp provides a 5.1v supply vo ltage from the internal ldo regulator from dcin and can deliver up to 30ma of continuous current. the mosfet drivers are powered by vddp. vddp also supplies power to vcc through a low pass filter as shown in ?typical application circuit? on page 2. bypass vddp and vcc with a 1f capacitor. vddsmb supply the vddsmb input provides power to the smbus interface. connect vddsmb to vcc, or apply an external supply to vddsmb. bypass vddsmb to gnd with a 0.1f or greater ceramic capacitor. the typical application connects vddsmb to the same power source as the smbus master. this supply should be active and greater than 2.5v when either the adapter or the battery is present. isl88731c does not function when vddsmb is below its specified under voltage lockout (uvlo) voltage. all of the smbus registers in isl88731c are powered by vddsmb and are set to zero when it is below the uvlo threshold. other functions are unpredictable when vddsmb is below the uvlo threshold. short circuit protection and 0v battery charging since the battery charger will regulate the charge current to the limit set by the chargecurrent regi ster, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery. undervoltage trickle charge folds back current if there is a short circuit on the output. undervoltage detect and battery trickle charging if the voltage at cson falls below 2.5v isl88731c reduces the charge current limit to 128ma to trickle charge the battery. when the voltage rises above 2.7v, the charge current reverts to the programmed value in the chargecurrent register. icm 20 i input r s1 ?? = (eq. 1)
isl88731c 12 fn6978.3 june 8, 2011 over-temperature protection if the die temp exceeds +150c, it stops charging. once the die temp drops below +125c, char ging will start up again. overvoltage protection isl88731c has an overvoltage protection circuit that limits the output voltage when the battery is removed or disconnected by a pulse charging circuit. if cson exceeds the output voltage set point in the charge voltage register by more than 300mv, an internal comparator pulls vcomp down and turns off both upper and lower fets of the buck as in figure 17. there is a delay of approximately 1s between v out exceeding the ovp trip point and pulling vcomp, lgate and ugate low. after ugate and lgate are turned off, inductor current continues to flow through the body diode of the lower fet and v out continues to rise until inductor current reaches zero. the system management bus the system management bus (smbus) is a 2-wire bus that supports bidirectional communications. the protocol is described briefly here. more detail is available from www.smbus.org . general smbus architecture data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 18. start and stop conditions as shown in figure 19, start condition is a high-to-low transition of the sda line while scl is high. the stop condition is a low-to-h igh transition on the sda line while scl is high. a stop condition must be sent before each start condition. figure 17. overvoltage protection in isl88731c inductor current v out phase battery current vddsmb sda scl output input scl control smbus master cpu sda control to other slave devices output input state machine, registers, memory, etc output input scl control sda control output input smbus slave state machine, registers, memory, etc output input scl control sda control output input smbus slave sda scl data line stable data valid change of data allowed figure 18. data validity sda scl start condition figure 19. start and stop waveforms stop condition sp
isl88731c 13 fn6978.3 june 8, 2011 acknowledge each address and data transmis sion uses 9-clock pulses. the ninth pulse is the acknowledge bit (ack). after the start condition, the master sends 7- slave address bits and a r/w bit during the next 8-clock pulses. du ring the ninth clock pulse, the device that recognizes its own address holds the data line low to acknowledge. the acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data (see figure 20). smbus transactions all transactions start with a contro l byte sent from the smbus master device. the control byte begins with a start condition, followed by 7-bits of slave address (0001001 for the isl88731c) followed by the r/w bit. the r/w bit is 0 for a write or 1 for a read. if any slave devices on the smbus bus recognize their address, they will acknowledge by pulling the serial data (sda) line low for the la st clock cycle in the control byte. if no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a not acknowledge condition. once the control byte is sent, and the isl88731c acknowledges it, the 2nd byte sent by the master must be a register address byte such as 0x14 for the chargecurrent register. the register address byte tells the isl88731c which register the master will write or read. see table 1 for details of the registers. once the isl88731c receives a register addr ess byte it responds with an acknowledge. byte format every byte put on the sda line must be eight bits long and must be followed by an acknowledge bi t. data is transferred with the most significant bit first (msb) an d the least significant bit last (lsb). isl88731c and smbus the isl88731c receives control inputs from the smbus interface. the serial interface complies with the smbus protocols as documented in the system management bus specification v1.1, which can be downloaded from www.smbus.org . the isl88731c uses the smbus read-word and write-word protocols (figure 21) to communicate with the smart battery. the isl88731c is an smbus slave device and does not initiate communication on the bus. it responds to the 7-bit address 0b0001001_ (0x12). read address = 0b00010011 and write address = 0b00010010. in addition, the isl88731c has two identification (id) registers: a 16-bit device id register and a 16-bit manufacturer id register. sda scl figure 20. acknowledge on the i 2 c bus 1 2 8 9 acknowledge msb from slave start table 1. battery charger register summary register address register name read/w rite description por state 0x14 chargecurrent read or write 6-bit charge current setting 0x0000 0x15 chargevoltage read or write 11-bit charge voltage setting 0x0000 0x3f inputcurrent read or write 6-bit charge current setting 0x0080 0xfe manufacturerid read only manufacturer id 0x0049 0xff deviceid read only device id 0x0001 figure 21. smbus/isl88731c read and write protocol a s a n p slave addr + w register addr hi byte data lo byte data a a a s a p slave addr + w register addr hi byte data lo byte data a a n s a slave addr + r p acknowledge no acknowledge sstart pstop driven by the master driven by isl88731c write to a register read from a register
isl88731c 14 fn6978.3 june 8, 2011 the data (sda) and clock (scl) pi ns have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors for sda and scl to achieve rise times according to the smbus specifications. the isl88731c is controlled by the data written to the registers described in table 1. battery charger registers the isl88731c supports five battery-charger registers that use either write-word or read-word protocols, as summarized in table 1. manufacturerid and deviceid are ?read only? registers and can be used to identify the isl88731c. on the isl88731c, manufacturerid always returns 0x0049 (ascii code for ?i? for intersil) and deviceid always returns 0x0001. enabling and disabling charging after applying power to isl88731c, the internal registers contain their por values (see table 1). the por values for charge current and charge voltage are 0x0000. th ese values disable charging. to enable charging, the chargecu rrent register must be written with a number >0x007f and the ch argevoltage register must be written with a number >0x000f. charging can be disabled by writing 0x0000 to either of these registers. setting charge voltage charge voltage is set by writing a valid 16-bit number to the chargevoltage register. this 16 -bit number translates to a 65.535v full-scale voltage. th e isl88731c ignores the first 4 lsbs and uses the next 11 bits to set the voltage dac. the charge voltage range of the isl88731c is 1.024v to 19.200v. numbers requesting charge voltag e greater than 19.200v result in a chargevoltage of 19.200v. all numbers requesting charge voltage below 1.024v result in a voltage set point of zero, which terminates charging. upon initial power-up or reset, the chargevoltage and chargecurrent registers are reset to 0 and the charger remains shut down until valid numbers are sent to the chargevoltage and chargecurrent registers. use the write- word protocol (figure 21) to write to the chargevoltage register. the register address for chargevoltage is 0x15. the 16-bit binary number formed by d15?d0 represents the charge voltage set point in mv. however, the resolution of the isl88731c is 16mv because the d0?d3 bits are ignored as shown in table 2. the d15 bit is also ignored because it is not needed to span the 1.024v to 19.2v range. table 2 shows the mapping between the charge-voltage set point and the 16-bit number written to the chargevoltage register. the charge voltage register can be read back to verify its contents. table 2. chargevoltage (register 0x15) bit bit name description 0not used. 1not used. 2not used. 3not used. 4 charge voltage, dacv 0 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 16mv of charger voltage. 5 charge voltage, dacv 1 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 32mv of charger voltage. 6 charge voltage, dacv 2 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 64mv of charger voltage. 7 charge voltage, dacv 3 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 128mv of charger voltage. 8 charge voltage, dacv 4 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 256mv of charger voltage. 9 charge voltage, dacv 5 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 512mv of charger voltage. 10 charge voltage, dacv 6 0 = adds 0ma of charger voltage. 1 = adds 1024mv of charger voltage. 11 charge voltage, dacv 7 0 = adds 0mv of charger voltage. 1 = adds 2048mv of charger voltage. 12 charge voltage, dacv 8 0 = adds 0mv of charger voltage. 1 = adds 4096mv of charger voltage. 13 charge voltage, dacv 9 0 = adds 0mv of charger voltage. 1 = adds 8192mv of charger voltage. 14 charge voltage, dacv 10 0 = adds 0mv of charger voltage. 1 = adds 16384mv of charger voltage, 19200mv max. 15 not used. normally a 32768mv weight.
isl88731c 15 fn6978.3 june 8, 2011 setting charge current isl88731c has a 16-bit chargecu rrent register that sets the battery charging current. isl88731c controls the charge current by controlling the csop-cson voltage. the register?s lsb translates to 10v at cson-csop. with a 10m charge current r sense resistor (rs2 in ?typical application circuit? on page 2), the lsb translates to 1ma charge current. the isl88731c ignores the first 7 lsbs and uses the next 6 bits to control the current dac. the charge-current range of the isl88731c is 0a to 8.064a (using a 10m current-sense resi stor). all numbers requesting charge current abov e 8.064a result in a current setting of 8.064a. all numbers requesting charge current between 0ma to 128ma result in a current setting of 0ma. the default charge current setting at power-on reset (por) is 0ma. to stop charging, set chargecurrent to 0. upon initial power up, the chargevoltage and chargecurr ent registers are reset to 0 and the charger is disabled. to start the charger, write valid numbers to the chargevoltage and chargecurrent registers. the chargecurrent register uses the write-word protocol (figure 21). the register code for chargecurrent is 0x14 (0b00010100). table 3 shows the mapping betwee n the charge current set point and the chargecurrent number. the chargecurrent register can be read back to verify its contents. the isl88731c includes a fault limiter for low battery conditions. if the battery voltage is less than 2.5v, the charge current is temporarily set to 128ma. the chargecurrent register is preserved and becomes active again when the battery voltage is higher than 2.7v. this function effectively provides a foldback current limit, which protects the charger during short circuit and overload. table 3. charge current (register 0x14) (10m sense resistor, rs2) bit bit name description 0not used. 1not used. 2not used. 3not used. 4not used. 5not used. 6not used. 7 charge current, daci 0 0 = ad ds 0ma of charger current. 1 = adds 128ma of charger current. 8 charge current, daci 1 0 = ad ds 0ma of charger current. 1 = adds 256ma of charger current. 9 charge current, daci 2 0 = ad ds 0ma of charger current. 1 = adds 512ma of charger current. 10 charge current, daci 3 0 = adds 0ma of charger current. 1 = adds 1024ma of charger current. 11 charge current, daci 4 0 = adds 0ma of charger current. 1 = adds 2048ma of charger current. 12 charge current, daci 5 0 = adds 0ma of charger current. 1 = adds 4096ma of charger current, 8064ma max. 13 not used. 14 not used. 15 not used.
isl88731c 16 fn6978.3 june 8, 2011 setting input-current limit the total power from an ac adapter is the sum of the power supplied to the system and the power into the charger and battery. when the input current exceeds th e set input current limit, the isl88731c decreases the charge current to provide priority to system load current. as the system load rises, the available charge current drops linearly to zero. th ereafter, the total input current can increase to the limit of the ac adapter. the internal amplifier compares the differential voltage between cssp and cssn to a scaled vo ltage set by the inputcurrent register. the total input current is the sum of the device supply current, the charger input current, and the system load current. the total input current can be estimated as shown in equation 2. where is the efficiency of the dc/dc converter (typically 85% to 95%). the isl88731c has a 16-bit inputcur rent register that translates to a 2ma lsb and a 131.071a full scale current using a 10m current-sense resistor (rs1 in figure 4). equivalently, the 16-bit inputcurrent number sets the voltage across cssp and cssn inputs in 20v per lsb increments . to set the input current limit use the smbus to write a 16-bit inputcurrent register using the data format listed in table 4. the inputcurrent register uses the write-word protocol (see figure 21). the register code for inputcurrent is 0x3f (0b00111111). the inputcurrent register can be read back to verify its contents. the isl88731c ignores the first 7 lsbs and uses the next 6 bits to control the input-current dac. the input-current range of the isl88731c is from 256ma to 11.004a. all 16-bit numbers requesting input current above 11.004a result in an input- current setting of 11.004a. all 16-bit numbers requesting input current between 0ma to 256ma result in an input-current setting of 0ma. the default input-current-limit setting at por is 256ma. when choosing the current-sense resistor rs1, carefully calculate its power rating. take into account variations in the system?s load current and the overall accuracy of the sense amplifier. note that the volt age drop across rs1 contributes additional power loss, which reduces efficiency. system currents normally fluctuate as portions of the system are powered up or put to sleep. without input current regulation, the input source must be able to deliver the maximum system current and the maximum charger-input current. by using the input-current-limit circuit, the output-current capab ility of the ac wall adapter can be lowered, reducing system cost. i input i system i charge v battery () v in () ? [] + = (eq. 2) table 4. input current (register 0x3f) (10m sense resistor, rs1) bit bit name description 0not used. 1not used. 2not used. 3not used. 4not used. 5not used. 6not used. 7 input current, dacs 0 0 = adds 0ma of input current. 1 = adds 256ma of input current. 8 input current, dacs 1 0 = adds 0ma of input current. 1 = adds 512ma of input current. 9 input current, dacs 2 0 = adds 0ma of input current. 1 = adds 1024ma of input current. 10 input current, dacs 3 0 = adds 0ma of input current. 1 = adds 2048ma of input current. 11 input current, dacs 4 0 = adds 0ma of input current. 1 = adds 4096ma of input current. 12 input current, dacs 5 0 = adds 0ma of input current. 1 = adds 8192ma of input current, 11004ma max. 13 not used. 14 not used. 15 not used.
isl88731c 17 fn6978.3 june 8, 2011 charger timeout the isl88731c includes 2 timers to insure the smbus master is active and to prevent overcharging the battery. isl88731c will terminate charging if the charger has not received a write to the chargevoltage or chargecurrent re gister within 175s or if the scl line is low for more than 25ms. if a time-out occurs, either chargevoltage or chargecurrent re gisters must be written to re- enable charging. isl88731c data byte order each register in isl88731c contains 16-bits or 2, 8 bit bytes. all data sent on the smbus is in 8-bit bytes and 2 bytes must be written or read from each regist er in isl88731c. the order in which these bytes are transmitted appears reversed from the way they are normally written. the low byte is sent first and the hi byte is sent second. for example, when writing 0x41a0, 0xa0 is written first and 0x41 is sent second. writing to the internal registers in order to set the charge current, charge voltage or input current, valid 16-bit numbers must be written to isl88731c?s internal registers via the smbus. to write to a register in the isl88731c, the master sends a control byte with the r/w bit set to 0, indicating a write. if it receives an acknowledge from the isl88731c it sends a register address byte setting the register to be written (i.e., 0x14 for the chargecurrent register). the isl88731c will respond with an acknowledge. the master then sends the lower data byte to be written into the desired register. the isl88731c will respond with an acknowledge. the master then sends the higher data byte to be written into the desired register. the isl88731c will respond with an acknowledge. the master then issues a stop condition, indicating to the isl88731c that the current transaction is complete. once this transaction completes the isl88731c will begin operating at the new current or voltage. isl88731c does not support writing more than one register per transaction. reading from the internal registers the isl88731c has the ability to re ad from 5 internal registers. prior to reading from an internal register, the master must first select the desired register by writing to it and sending the registers address byte. this process begins by the master sending a control byte with the r/w bit set to 0, indicating a write. once it receives an acknowledge from the isl88731c it sends a register address byte representing the internal register it wants to read. the isl88731c will respond with an acknowledge. the master must then respond with a stop conditio n. after the stop condition the master follows with a new start condition, then sends a new control byte with the isl887 31c slave address and the r/w bit set to 1, indicating a read. the isl88731c will acknowledge then send the lower byte stored in that register. after receiving the byte, the master acknowledges by holding sda low during the 9th clock pulse. isl88731c then sends the high er byte stored in the register. after the second byte neither device holds sda low (no acknowledge). the master will then produce a stop condition to end the read transaction. isl88731c does not support reading more than 1 register per transaction. application information the following battery charger design refers to the ?typical application circuit? (see figure 4), where typical battery configuration of 3s2p is used. this section describes how to select the external components including the inductor, input and output capacitors, switching mosfets and current sensing resistors. inductor selection the inductor selection has tr ade-offs between cost, size, crossover frequency and efficiency. for example, the lower the inductance, the smaller the size, bu t ripple current is higher. this also results in higher ac losses in the magnetic core and the windings, which decreases the system efficiency. on the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher dcr (dc resistance of the inductor) loss, lower saturation current and has slower transient response. so, th e practical inductor design is based on the inductor ripple curre nt being 15% to 20% of the maximum operating dc current at maximum input voltage. maximum ripple is at 50% duty cycle or v bat =v in,max /2. the required inductance for 15% ripp le current can be calculated from equation 3: where v in,max is the maximum input voltage, f sw is the switching frequency and i l,max is the max dc current in the inductor. for v in,max = 20v, v bat = 12.6v, i bat,max = 4.5a, and f s = 400khz, the calculated induct ance is 9.3h. choosing the closest standard value gives l = 10h. ferrite cores are often the best choice since they are optimized at 400khz to 600khz operation with low core loss. the core must be large enough not to saturate at the peak inductor current i peak in equation 4: inductor saturation can lead to cascade failures due to very high currents. conservative design limits the peak and rms current in the inductor to less than 90% of the rated saturation current. crossover frequency is heavily dependent on the inductor value. f co should be less than 20% of the switching frequency and a conservative design has f co less than 10% of the switching frequency. the highest f co is in voltage control mode with the battery removed and may be calculated (approximately) from equation 5: l v in max , 4f sw 0.3 i ? lmax , ?? ------------------------------------------------------ - = (eq. 3) i peak i lmax , 1 2 --- + i ripple ? = (eq. 4) f co 511rs2 ?? 2 l ? ------------------------------ - = (eq. 5)
isl88731c 18 fn6978.3 june 8, 2011 output capacitor selection the output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. the rms value of the output ripple current i rms is given by equation 6: where the duty cycle d is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. during the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. so, the duty cycle varies from 0.53 for the minimum battery voltage of 7.5v (2.5v/cell) to 0.88 for the maximum battery voltage of 12.6v. the maximum rms value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as equation 7: for v in,max = 19v, vbat = 16.8v, l = 10h, and f s =400khz, the maximum rms current is 0.19a. a typical 20f ceramic capacitor is a good choice to absorb this current and also has very small size. organic polymer capacitors have high capacitance with small size and have a significant equivalent series resistance (esr). although esr adds to ripple voltage, it also creates a high frequency ze ro that helps the closed loop operation of the buck regulator. emi considerations usually make it desirable to minimize ripple current in the battery leads. beads may be added in series with the battery pack to increase the battery impedance at 400khz switching frequency. switching ripple current splits between the battery and the output capacitor depending on the esr of the output capacitor and battery impeda nce. if the esr of the output capacitor is 10m and battery impedance is raised to 2 with a bead, then only 0.5% of the ripple current will flow in the battery. mosfet selection the notebook battery charger synchronous buck converter has the input voltage from the ac-adapter output. the maximum ac-adapter output voltage does not exceed 25v. therefore, 30v logic mosfet should be used. the high-side mosfet must be able to dissipate the conduction losses plus the switching lo sses. for the battery charger application, the input voltage of the synchronous buck converter is equal to the ac-adapter output voltage, which is relatively constant. the maximum efficiency is achieved by selecting a high side mosfet that has the conducti on losses equal to the switching losses. switching losses in the lo w-side fet are very small. the choice of low-side fet is a trade-off between conduction losses (r ds(on) ) and cost. a good rule of thumb for the r ds(on) of the low-side fet is 2x the r ds(on) of the high-side fet. the lgate gate driver can drive sufficient gate current to switch most mosfets efficiently. howeve r, some fets may exhibit cross conduction (or shoot-through) due to current injected into the drain-to-source parasitic capacitor (c gd ) by the high dv/dt rising edge at the phase node when the high side mosfet turns on. although lgate sink current (1.8a typical) is more than enough to switch the fet off quickly, voltage drops across parasitic impedances between lgate and the mosfet can allow the gate to rise during the fast rising edge of voltage on the drain. mosfets with low threshold voltage (<1.5v) and low ratio of c gs /c gd (<5) and high gate resistance (>4 ) may be turned on for a few ns by the high dv/dt (rising edge) on their drain. this can be avoided with higher threshold voltage and c gs /c gd ratio. another way to avoid cross conduction is slowing the turn-on speed of the high-side mosfet by connecting a resistor between the boot pin and the bootstrap capacitor. for the high-side mosfet, the worst-case conduction losses occur at the minimum input voltage, as shown in equation 8: the optimum efficiency occurs when the switching losses equal the conduction losses. however, it is difficult to calculate the switching losses in the high-side mosfet since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. these factors include the mosfet internal gate resistance, gate charge, threshol d voltage, stray inductance and the pull-up and pull-down resistance of the gate driver. the following switching loss calculation (equation 9) provides a rough estimate. where the following are the peak gate-drive source/sink current of q 1 , respectively: ?q gd : drain-to-gate charge, ?q rr : total reverse recovery charge of the body-diode in low-side mosfet, ?i lv : inductor valley current, ?i lp : inductor peak current, ?i g,sink ?i g , source low switching loss requires low drain-to-gate charge q gd . generally, the lower the drain- to-gate charge, the higher the on-resistance. therefore, there is a trade-off between the on-resistance and drain-to-gate charge. good mosfet selection is based on the figure of merit (fom), which is a product of the total gate charge and on-resistance. usually, the smaller the value of fom, the higher the efficiency for the same application. for the low-side mosfet, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage as shown in equation 10. choose a low-side mosfet that has the lowest possible on-resistance with a moderate-sized package (like the 8 ld soic) and is reasonably priced. the switching losses are not an issue for the low-side mosfet because it operates at zero-voltage-switching. icout () rms v in max , 12 l f sw ?? ---------------------------------- d1d ? () ?? = (eq. 6) icout () rms v in max , 412lf sw ??? ------------------------------------------ = (eq. 7) p q1 conduction , v out v in ------------ - i bat 2 r ds on () ?? = (eq. 8) p q1 switching , 1 2 -- - v in i lv f sw q gd i gsource , ----------------------- - ?? ?? ?? 1 2 -- - v in i lp f sw q gd i gk sin , ---------------- - ?? ?? ?? q rr v in f sw + + = (eq. 9) p q2 1 v out v in ------------ - ? ?? ?? ?? i bat 2 r ds on () ?? = (eq. 10)
isl88731c 19 fn6978.3 june 8, 2011 ensure that the required total ga te drive current for the selected mosfets should be less than 24ma. thus, the total gate charge for the high-side and low-side mosfets is limited by equation 11: where i gate is the total gate drive current and should be less than 24ma. substituting i gate =24ma and f s =400khz into equation 11 yields that the total gate charge should be less than 80nc. therefore, the isl88731c easily drives the battery charge current up to 8a. snubber design isl88731c's buck regulator operates in discontinuous current mode (dcm) when the load cu rrent is less than half the peak-to-peak current in the inductor. after the low-side fet turns off, the phase voltage rings due to the high impedance with both fets off. this can be seen in figure 11. adding a snubber (resistor in series with a capa citor) from the phase node to ground can greatly re duce the ringing. in some situations, a snubber can improve output ripple and regulation. the snubber capacitor should be approximately twice the parasitic capacitance on the phase node. this can be estimated by operating at very low load current (100ma) and measuring the ringing frequency. c snub and r snub can be calculated from equations 12 and 13: input capacitor selection the input capacitor absorbs the ripple current from the synchronous buck converter, which is given by equation 14: this rms ripple current must be smaller than the rated rms current in the capacitor data sheet. non-tantalum chemistries (ceramic, aluminum, or oscon) are preferred due to their resistance to power-up surge cu rrents when the ac-adapter is plugged into the battery charger. for notebook battery charger applications, it is recommended that ceramic capacitors or polymer capacitors from sanyo be used due to their small size and reasonable cost. loop compensation design isl88731c has three closed loop control modes. one controls the output voltage when the battery is fully charged or absent. a second controls the current into the battery when charging and the third limits current drawn fr om the adapter. the charge current and input current control loops are compensated by a single capacitor on the icomp pin. the voltage control loop is compensated by a network on the vcomp pin. descriptions of these control loops and guidelin es for selecting compensation components will be given in the following sections. which loop controls the output is determined by the minimum current buffer and the minimum voltage buffer shown in the ?functional block diagram? on page 2. these three loops will be described separately. transconductance amplifiers gmv, gmi and gms isl88731c uses several transconductance amplifiers (also known as gm amps). most commer cially available op amps are voltage controlled voltage sources with gain expressed as a=v out /v in . gm amps are voltage co ntrolled current sources with gain expressed as gm = i out /v in . gm will appear in some of the equations for poles and zeros in the compensation. pwm gain f m the pulse width modulator in the isl88731c converts voltage at vcomp to a duty cycle by comparing vcomp to a triangle wave (duty = vcomp/v p-p ramp ). the low-pass filter formed by l and c o convert the duty cycle to a dc output voltage (vo = v dcin *duty). in isl88731c, the triangle wave amplitude is proportional to v dcin . making the ramp am plitude proportional to dcin makes the gain from vcomp to the phase output a constant 11 and is independent of dcin. for small signal ac analysis, the battery is modeled by its internal resistance. the total output resistance is the su m of the sense resistor and the internal resistance of the mosfets, inductor and capacitor. figure 22 shows the small sign al model of the pulse width modulator (pwm), power stage, output filter and battery. in most cases the battery resi stance is very small (<200m ) resulting in a very low q in the output filter. this results in a frequency response from the input of the pwm to the inductor current with a single pole at the frequency calculated in equation 15: q gate i gate f sw -------------- (eq. 11) c snub 2 2 f ring () 2 l ? ----------------------------------- - = (eq. 12) r snub 2l ? c snub ----------------- = (eq. 13) (eq. 14) i rms i bat v out v in v out ? () v in -------------------------------------------------- = figure 22. small signal ac model drivers ramp gen v ramp = v adapter /11 v adapter - + 11 pwm input l c o l r esr c o rs2 r bat r fet_rdson pwm input r l_dcr pwm gain = 11 f pole1 rs2 r ds on () r dcr r bat +++ () 2 l ? ------------------------------------------------------------------------------------ - = (eq. 15)
isl88731c 20 fn6978.3 june 8, 2011 the output capacitor creates a pole at a very high frequency due to the small resistance in parallel with it. the frequency of this pole is calculated in equation 16: charge current control loop when the battery is less than the fully charged, the voltage error amplifier goes to it?s maximum output (limited to 0.3v above icomp) and the icomp voltage controls the loop through the minimum voltage buffer. figure 24 shows the charge current control loop. the compensation capacitor (c icomp ) gives the error amplifier (gmi) a pole at a very low frequency (<<1hz) and a zero at f z1 . f z1 is created by the 0.25*ca2 output added to icomp. the frequency can be calculated from equation 17: placing this zero at a frequency equal to the pole calculated in equation 16 will result in maximum gain at low frequencies and phase margin near 90. if the zero is at a higher frequency (smaller c icomp ), the dc gain will be higher but the phase margin will be lower. use a capacitor on icomp that is equal to or greater than the value calculated in equation 18. the factor of 1.5 is to ensure the zero is at a frequency lower than the pole including tolerance variations. a filter should be added between r s2 and csop and cson to reduce switching noise. the filter roll-off frequency should be between the crossover frequency and the switching frequency (~100khz). r f2 should be small (<10 ) to minimize offsets due to leakage current into csop. the filter cutoff frequency is calculated using equation 19: the crossover frequency is determined by the dc gain of the modulator and output filter and the pole in equation 16. the dc gain is calculated in equation 20 and the cross over frequency is calculated with equation 21: the bode plot of the loop gain , the compensator gain and the power stage gain is shown in figure 24. adapter current limit control loop if the combined battery charge current and system load current draws current that equals the adapter current limit set by the inputcurrent register, isl88731c will reduce the current to the battery and/or reduce the output voltage to hold the adapter current at the limit. above the adapter current limit the minimum current buffer equals the output of gms and icomp controls the charger output. figure 25 shows th e adapter current limit control loop. f pole2 1 2 c o r bat ?? ------------------------------------ = (eq. 16) (eq. 17) f zero 4gm2 ? 2 c icomp ? () ------------------------------------ - = gm2 50 av ? = figure 23. charge current limit loop r s2 r bat icomp cson phase r esr c o 11 + - 20x csop s + - 0.25 daci + - gmi c f2 r f2 c icomp l r fet_rdson r l_dcr ca2 c icomp 1.5 4 50 av ? () l ?? ? rs2 r ds on () r dcr r bat +++ () ------------------------------------------------------------------------------------ - = (eq. 18) f filter 1 2 c f2 r f2 ?? () ---------------------------------------- - = (eq. 19) a dc 11 rs2 ? rs2 r ds on () r dcr r bat +++ () ------------------------------------------------------------------------------------ - = (eq. 20) f co a dc f pole ? 11 rs2 ? 2 l ? ---------------------- - == (eq. 21) figure 24. charge current loop bode plots -60 -40 -20 0 20 40 60 0.01k 0.1k 1k 10k 100k 1m frequency (hz) gain (db) compensator modulator loop f pole2 f filter f pole1 f zero c icomp r bat icomp phase 11 s + - 0.25 dacs + - gms r s1 dcin cssn + - ca1 20 cssp c f1 r f1 r s2 cson + - 20x csop c f2 r f2 r esr c o l r fet_rdson r l_dcr ca2 figure 25. adapter current limit loop
isl88731c 21 fn6978.3 june 8, 2011 the loop response equations, bo de plots and the selection of c icomp are the same as the charge cu rrent control loop with loop gain reduced by the duty cycle and the ratio of r s1 /r s2 . in other words, if r s1 = r s2 and the duty cycle d = 50%, the loop gain will be 6db lower than the loop gain in figure 25. this gives lower crossover frequency and higher ph ase margin in this mode. if r s1 /r s2 = 2 and the duty cycle is 50% then the adapter current loop gain will be identical to the gain in figure 25. a filter should be added between r s1 and csip and csin to reduce switching noise. the filter roll of f frequency should be between the cross over frequency and the switching frequency (~100khz). voltage control loop when the battery is charged to the voltage set by chargevoltage register, the voltage error amplifier (gmv) takes control of the output (assuming that the adapte r current is below the limit set by aclim). the voltage error amplifier (gmv) discharges the cap on vcomp to limit the output voltage. the current to the battery decreases as the cells charge to the fixed voltage and the voltage across the internal battery resistance decreases. as battery current decreases the 2 current error amplifiers (gmi and gms) output their maximum current and charge the capacitor on icomp to its maximum voltage (limited to 0.3v above vcomp). with high voltage on icomp, the minimum voltage buffer output equals the voltage on vcomp. the voltage control loop is shown in figure 26. output lc filter transfer functions the gain from the phase node to the system output and battery depend entirely on external components. typical output lc filter response is shown in figure 27. transfer function a lc (s) is shown in equation 22: the resistance r o is a combination of mosfet r ds(on) , inductor dcr, r sense and the internal resistance of the battery (normally between 50m and 200m ) the worst case for voltage mode control is when the battery is absent. this results in the highest q of the lc filter and the lowest phase margin. the compensation network consists of the voltage error amplifier gmv and the compensation network r vcomp , c vcomp which give the loop very high dc gain, a ve ry low frequency pole and a zero at f zero1 . inductor current information is added to the feedback to create a second zero f zero2 . the low pass filter r f2 , c f2 between r s2 and isl88731c add a pole at f filter . r 3 and r 4 are internal divider resistors that set the dc output voltage. for a 3-cell battery, r 3 = 500k and r 4 = 100k . the following equations relate the compensati on network?s poles, zeros and gain to the components in figure 26. figure shows an asymptotic bode plot of the dc/dc converter?s gain vs. frequency. it is strongly recommended that f zero1 is approximately 30% of f lc and f zero2 is approximately 70% of f lc . figure 26. voltage control loop vcomp cson phase 11 csop s + - 0.25 + - gmv c vcomp r vcomp dacv r3 r4 + - 20x r s2 r bat r esr c o c f2 r f2 l r fet_rdson r l_dcr ca2 a lc 1 s esr ------------- - ? ?? ?? s 2 dp ---------- - s lc q ? () ----------------------- 1 ++ ?? ?? ?? -------------------------------------------------------- - = esr 1 r esr c o ? () ----------------------------- = lc 1 lc o ? () ---------------------- - = qr o l c o ----- - ? = (eq. 22) figure 27. frequency response of the lc output filter phase () gain (db) frequency (hz) no battery r battery = 200m ? r battery = 50m ?
isl88731c 22 fn6978.3 june 8, 2011 compensation break frequency equations choose r vcomp equal or lower than the value calculated from equation 29. next, choose c vcomp equal or higher than the value calculated from equation 30. pcb layout considerations power and signal layers placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. as an example, layer arrangement on a 4-layer board is shown in the following: 1. top layer: signal lines, or half board for signal lines and the other half board for power lines 2. signal ground 3. power layers: power ground 4. bottom layer: power mosfet, inductors and other power traces separate the power voltage and current flowing path from the control and logic level signal path. the controller ic will stay on the signal layer, which is isolated by the signal ground to the power signal traces. component placement the power mosfet should be close to the ic so that the gate drive signal, the lgate, ugate, phase, and boot, traces can be short. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. signal ground and power ground connection at minimum, a reasonably large area of copper, which will shield other noise couplings through the ic, should be used as signal ground beneath the ic. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the ic is not recommended. gnd and vcc pin at least one high quality ceramic decoupling capacitor should be used to cross these two pins. the decoupling capacitor can be put close to the ic. lgate pin this is the gate drive signal for the bottom mosfet of the buck converter. the signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. these two traces should be short, wide, and away from other traces. there should be no other traces in parallel with these traces on any layer. pgnd pin pgnd pin should be laid out to the negative side of the relevant output capacitor with separate tr aces. the negative side of the output capacitor must be close to the source node of the bottom mosfet. this trace is the return path of lgate. -60 -40 -20 0 20 40 60 0.1k 1k 10k 100k 1m frequency (hz) gain (db) compensator modulator loop f zero1 f zero2 f filter f esr f pole1 f lc figure 28. asymptotic bode plot of the voltage control loop gain f zero1 1 2 c vcomp r vcomp ?? () ---------------------------------------------------------------- - = (eq. 23) f zero2 r vcomp 2 rs2 c ? o ? --------------------------------- - ?? ?? ?? r 4 r 4 r 3 + -------------------- ?? ?? ?? gm1 5 ------------ ?? ?? ?? = (eq. 24) f lc 1 2 lc o ? () ------------------------------ = (eq. 25) f filter 1 2 r f2 c f2 ?? () ---------------------------------------- - = (eq. 26) f pole1 1 2 rs2 c o ?? () -------------------------------------- - = (eq. 27) f esr 1 2 c o r esr ?? () ----------------------------------------- = (eq. 28) r vcomp 0.7 f lc ? () 2 c o rs2 ?? () 5 gm1 ------------ ?? ?? r 3 r 4 + r 4 -------------------- ?? ?? ?? ??? = (eq. 29) c vcomp 1 0.3 f lc ? () 2 r vcomp ? () ? ---------------------------------------------------------------------- = (eq. 30)
isl88731c 23 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6978.3 june 8, 2011 for additional products, see www.intersil.com/product_tree phase pin this trace should be short, and positioned away from other weak signal traces. this node has a very high dv/dt with a voltage swing from the input voltage to ground. no trace should be in parallel with it. this trace is al so the return path for ugate. connect this pin to the high-side mosfet source. ugate pin this pin has a square shape waveform with high dv/dt. it provides the gate drive current to charge and discharge the top mosfet with high di/dt. this trace should be wide, short, and away from other traces, similar to the lgate. boot pin this pin?s di/dt is as high as the ugate; therefore, this trace should be as short as possible. csop, cson, cssp and cssn pins accurate charge current and adap ter current sensing is critical for good performance. the curren t sense resistor connects to the cson and the csop pins through a low pass filter with the filter capacitor very near the ic (see figure 4). traces from the sense resistor should start at the pads of the sense resistor and should be routed close together, through the low pass filter and to the csop and cson pins (see figure 29). the cson pin is also used as the battery voltage feedback. the traces should be routed away from the high dv/dt and di/dt pins like phase, boot pins. in general, the current sense resi stor should be close to the ic. these guidelines should also be followed for the adapter current sense resistor and cssp and cssn. other layout arrangements should be adjusted accordingly. dcin pin this pin connects to ac-adapter output voltage, and should be less noise sensitive. copper size for the phase node the capacitance of phase should be kept very low to minimize ringing. it would be best to lim it the size of the phase node copper in strict accordance with the current and thermal management of the application. identify the power and signal ground the input and output capacitors of the converters, the source terminal of the bottom switching mosfet pgnd should connect to the power ground. the other components should connect to signal ground. signal and power gr ound are tied together at one point. clamping capacitor for switching mosfet it is recommended that ceramic capacitors be used closely connected to the drain of the high-side mosfet, and the source of the low-side mosfet. this capacitor reduces the noise and the power loss of the mosfet. figure 29. current sense resistor layout high current trace high current trace kelvin connection traces to the low pass filter and csop and cson sense resistor
isl88731c 24 fn6978.3 june 8, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl88731c to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/25/11 fn6978.3 removed icm offset spec line from ec table removed upper and lower icm gain limits changed elect specs note 7, from: "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design? to: parameters with min and/or max limits are 100% tested at +25c, un less otherwise specified. temperature limits established by characterizati on and are not production tested. 1/14/11 fn6978.2 revised ?vddsmb supply? on page 11 from: ?the vddsmb input provides power to the smbus interface. connect vddsmb to vcc, or apply an external supply to vddsmb to keep the smbus interface active while the supply to dcin is removed. when vddsmb is biased the internal registers are maintained. bypa ss vddsmb to gnd with a 0.1f or greater ceramic capacitor.? to: ?the vddsmb input provides power to the smbus interface. connect vddsmb to vcc, or apply an external supply to vddsmb. bypass vddsmb to gnd with a 0.1f or greater ceramic capacitor. the typical application connects vddsmb to the same po wer source as the smbus master. this supply should be active and greater than 2.5v when eith er the adapter or the battery is present. isl88731c does not function when vdds mb is below its specified under voltage lockout (uvlo) voltage. all of the smbus registers in isl88731c are powered by vddsmb and are set to zero when it is below the uvlo threshold. other functions ar e unpredictable when vddsmb is below the uvlo threshold.? 12/9/10 vddsmb uvlo hysteresis limits u pdated to reflect actual test results from (100, 150, 200 mv) to (40, 100, 150mv) added to pin 3 vref pin description on page 3 ?it is internally compensated. do not connect a decoupling capacitor.? 12/3/10 -converted to new intersil template -updated related literature's application note's title to match application note -changed copyright to legal's suggested verbiage -on page 2, figure 3, functional block diagram, acok comparator input changed from ref to 3.2v. "ref" was a typo. -added eval board to ordering information -acok leakage current test condition in el ectrical spec table on page 7 changed from acin = 2.5v to 3.7v. 3.7v has always been the test condition on this part. -removed note: limits established by characterization and are not production tested (no longer an intersil standard) and all references to it in switching regulators ugate and lgate -changed note: parameters with min and/or max limits are 100% tested at +25c, un less otherwise specified. temperature limits established by characterizati on and are not production tested. to new standard note: compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. 8/23/10 fn6978.1 added ?overvoltage protection? on page 12 an d figure 17?overvoltage protection in isl88731c? to page 12. 3/8/10 fn6978.0 initial release.
isl88731c 25 fn6978.3 june 8, 2011 package outline drawing l28.5x5b 28 lead thin quad flat no-lead plastic package rev 1, 10/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 28x 0.55 0.05 4 a 28x 0.25 0.05 m 0.10 c b 14 8 4x 0.50 24x 3.0 6 pin #1 index area 3 .25 0 . 10 0 . 75 0.05 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 25) ( 4. 65 typ ) ( 24x 0 . 50) (28x 0 . 25 ) ( 28x 0 . 75) 15 22 21 7 1 28

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